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10 MHz, 20 V/s, G = 1, 10, 100, 1000 i CMOS(R) Programmable Gain Instrumentation Amplifier
Preliminary Technical Data
FEATURES
Small package: 10-lead MSOP Programmable gains: 1, 10, 100, 1000 Digital or pin-programmable gain setting Wide supply: 5 V to 15 V Excellent dc performance High CMRR 120 dB , G = 100 Low gain drift: 10 ppm/C Low offset drift: 1.2 V/C , G = 1000 Excellent ac performance Fast settling time: 615 ns to 0.001% High slew rate: 20 V/s Low distortion: High CMRR over frequency: 80 dB to 50 kHz Low noise: 8 nV/Hz, G = 1000 Low power: 4 mA
DGD -IN WR A1
AD8253
FUNCTIONAL BLOCK DIAGRAM
A0
Logic
OUT
+IN
AD8253
+VS
-VS
REF
Figure 1.
APPLICATIONS
Data acquisition Biomedical analysis Test and measurement
Table 1. Instrumentation and Difference Amplifiers by Category
High Performance AD82201 AD8221 AD8222 AD82241 Low Cost AD6231 AD85531 High Voltage AD628 AD629 Mil Grade AD620 AD621 AD524 AD526 AD624 Low Power AD6271 Digital Gain AD82311 AD8250 AD8251 AD85551 AD85561 AD85571
GENERAL DESCRIPTION
The AD8253 is an instrumentation amplifier with digitally programmable gains that has G input impedance, low output noise, and low distortion making it suitable for interfacing with sensors and driving high sample rate analog-to-digital converters (ADCs). It has high bandwidth of 10 MHz, low THD and fast settling time of 615 ns to 0.001%. Offset drift and gain drift are specified to 1.2 V/C and 10 ppm/C, respectively for G = 1000. In addition to its wide input common voltage range, it boasts a high common-mode rejection of 80 dB at G = 1 from dc to 50 kHz. The combination of precision dc performance coupled with high speed capabilities make the AD8253 an excellent candidate for data acquisition. Furthermore, this monolithic solution simplifies design and manufacturing, and boosts performance of instrumentation by maintaining a tight match of internal resistors and amplifiers. The AD8253 user interface consists of a parallel port that allows users to set the gain in one of two different ways (see Figure 1 for the functional block diagram). A 2-bit word sent via a bus can be latched using the WR input. An alternative is to use transparent gain mode where the state of logic levels at the gain port determines the gain.
1
Rail-to-rail output.
The AD8253 is available in a 10-lead MSOP package and is specified over the -40C to +85C temperature range, making it an excellent solution for applications where size and packing density are important considerations.
Rev. prA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2007 Analog Devices, Inc. All rights reserved.
AD8253 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Diagram ........................................................................... 5 Absolute Maximum Ratings............................................................ 6
Preliminary Technical Data
Maximum Power Dissipation ......................................................6 ESD Caution...................................................................................6 Pin Configuration and Function Descriptions..............................7 Theory of Operation .........................................................................8 Gain Selection................................................................................8 Outline Dimensions ....................................................................... 10 Ordering Guide .......................................................................... 10
REVISION HISTORY
4/07--Revision 0: Initial Version
Rev. prA | Page 2 of 10
Preliminary Technical Data SPECIFICATIONS
+VS = +15 V, -VS = -15 V, VREF = 0 V @ TA = 25C, G = 1, RL = 2 k, unless otherwise noted. Table 2.
Parameter COMMON-MODE REJECTION RATIO (CMRR) CMRR to 60 Hz with 1 k Source Imbalance G=1 G = 10 G = 100 G = 1000 CMRR to 50 kHz G=1 G = 10 G = 100 G = 1000 NOISE Voltage Noise, 1 kHz, RTI G=1 G = 10 G = 100 G = 1000 0.1 Hz to 10 Hz, RTI G=1 G = 10 G = 100 G = 1000 Current Noise, 1 kHz Current Noise, 0.1 Hz to 10 Hz VOLTAGE OFFSET Offset RTI VOS Over Temperature Average TC Offset Referred to the Input vs. Supply (PSR) INPUT CURRENT Input Bias Current Over Temperature Average TC Input Offset Current Over Temperature Average TC DYNAMIC RESPONSE Small Signal -3 dB Bandwidth G=1 G = 10 G = 100 G = 1000 Settling Time 0.01% G=1 G = 10 G = 100 G = 1000 Conditions +IN = -IN = -10 V to +10 V 80 100 120 120 +IN = -IN = -10 V to +10 V 80 Min Typ Max
AD8253
Unit
dB dB dB dB dB dB dB dB
40 9 8 8 2.5 2.5
nV/Hz nV/Hz nV/Hz nV/Hz V p-p V p-p V p-p V p-p pA/Hz pA p-p V V V/C V/V 30 40 400 30 30 160 nA nA pA/C nA nA pA/C
5 60 G = 1, 10, 100, 1000 T = -40C to +85C T = -40C to +85C VS = 5 V to 15 V 200 + 600/G 260 + 900/G 1.2 + 5/G 6 + 20/G 5 T = -40C to +85C 5 T = -40C to +85C
10 6 3 0.3 OUT = 10 V step 585 648
MHz MHz MHz MHz ns ns ns ns
Rev. prA | Page 3 of 10
AD8253
Parameter Settling Time 0.001% G=1 G = 10 G = 100 G = 1000 Slew Rate G=1 G = 10 G = 100 G = 1000 Total Harmonic Distortion GAIN Gain Range Gain Error G=1 G = 10 G = 100 G = 1000 Gain Nonlinearity G=1 G = 10 G = 100 G = 1000 Gain vs. Temperature INPUT Input Impedance Differential Common Mode Input Operating Voltage Range Over Temperature OUTPUT Output Swing Over Temperature Short-Circuit Current REFERENCE INPUT RIN IIN Voltage Range Gain to Output DIGITAL LOGIC Digital Ground Voltage, DGND Digital Input Voltage Low Digital Input Voltage High Digital Input Current Gain Switching Time1 tSU tHD t WR -LOW t WR -HIGH Conditions OUT = 10 V step Min
Preliminary Technical Data
Typ 615 685 Max Unit ns ns ns ns V/s V/s V/s V/s dB 1000 0.03 0.04 V/V % % % % ppm ppm ppm ppm ppm/C
20 25 25 25 f = 1 kHz, RL = 10 k, G = 1 G = 1, 10, 100, 1000 OUT = 10 V 1
OUT = -10 V to +10 V RL = 10 k, 2 k, 600 RL = 10 k, 2 k, 600 RL = 10 k, 2 k, 600 RL = 10 k, 2 k, 600 All gains
6 10
10
VS = 5 V to 15 V T = -40C to +85C
1 1 -VS + 1.0 -VS + 1.1 -13.5 -13.5 37 20
+VS - 1.1 +VS - 1.4 +13.5 +13.5
G||pF G||pF V V V V mA k A V V/V
T = -40C to +85C
+IN, -IN, REF = 0 -VS
1 +VS
1 0.0001
Referred to GND Referred to GND Referred to GND -VS + 4.25 DGND 2.8 0 +VS - 2.7 2.1 +VS 325 See Figure 2 timing diagram 20 10 20 40
1
V V V A ns ns ns ns ns
Rev. prA | Page 4 of 10
Preliminary Technical Data
Parameter POWER SUPPLY Operating Range Quiescent Current, +IS Quiescent Current, -IS Over Temperature TEMPERATURE RANGE Specified Performance
1
AD8253
Conditions Min 5 4.1 3.7 T = -40C to +85C -40 Typ Max 15 4.5 4.5 4.5 +85 Unit V mA mA mA C
Add time for the output to slew and settle to calculate the total time for a gain change.
TIMING DIAGRAM
tWR-HIGH
WR
tWR-LOW
tSU
A0, A1
tHD
06287-003
Figure 2. Timing Diagram for Latched Gain Mode (See the Timing for Latched Gain Mode Section)
Rev. prA | Page 5 of 10
AD8253 ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Supply Voltage Power Dissipation Output Short-Circuit Current Common-Mode Input Voltage Differential Input Voltage Digital Logic Inputs Storage Temperature Range Operating Temperature Range2 Lead Temperature (Soldering 10 sec) Junction Temperature JA (4-Layer JEDEC Standard Board) Package Glass Transition Temperature
1 2
Preliminary Technical Data
package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). Assuming the load (RL) is referenced to midsupply, the total drive power is VS/2 x IOUT, some of which is dissipated in the package and some in the load (VOUT x IOUT). The difference between the total drive power and the load power is the drive power dissipated in the package.
PD = Quiescent Power + (Total Drive Power - Load Power)
Rating 17 V See Figure 3 Indefinite1 VS VS VS -65C to +125C -40C to +85C 300C 140C 112C/W 140C
V V PD = (VS x I S ) + S x OUT 2 RL
VOUT 2 - RL
In single-supply operation with RL referenced to -VS, worst case is VOUT = VS/2. Airflow increases heat dissipation, effectively reducing JA. In addition, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduces the JA. Figure 3 shows the maximum safe power dissipation in the package vs. the ambient temperature on a 4-layer JEDEC standard board.
2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 -40
Assumes the load is referenced to mid supply. Temperature for specified performance is -40C to +85C. For performance to +125C, see the Error! Reference source not found. section.
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8253 package is limited by the associated rise in junction temperature (TJ) on the die. The plastic encapsulating the die locally reaches the junction temperature. At approximately 140C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8253. Exceeding a junction temperature of 140C for an extended period can result in changes in silicon devices, potentially causing failure. The still-air thermal properties of the package and PCB (JA), the ambient temperature (TA), and the total power dissipated in the package (PD) determine the junction temperature of the die. The junction temperature is calculated as
MAXIMUM POWER DISSIPATION (W)
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
-20
0
20
40
60
80
100
120
AMBIENT TEMPERATURE (C)
Figure 3. Maximum Power Dissipation vs. Ambient Temperature
ESD CAUTION
TJ = TA + (PD x JA )
The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the
Rev. prA | Page 6 of 10
06287-004
Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
-IN 1 DGND 2 -VS 3 A1 5
10
AD8253
2 3 4 5 6 7 8 9 10 DGND -VS A0 A1 WR OUT +VS REF +IN differential input. Digital Ground. Negative Supply Terminal. Gain Setting Pin (LSB). Gain Setting Pin (MSB). Write Enable. Output Terminal. Positive Supply Terminal. Reference Voltage Terminal. Noninverting Input Terminal. True differential input.
+IN VREF
AD8253
9
8 +VS TOP VIEW A0 4 (Not to Scale) 7 VOUT 6
WR
NC = NO CONNECT
Figure 4. 10-Lead MSOP (RM-10) Pin Configuration
Table 4. Pin Function Descriptions
Pin No. 1 Name -IN Description Inverting Input Terminal. True
Rev. prA | Page 7 of 10
AD8253 THEORY OF OPERATION
+VS +VS A0 2.2k +VS -IN 2.2k A1 -VS 10k 10k -VS -VS A1
Preliminary Technical Data
+VS DIGITAL GAIN CONTROL
A3 -VS +VS
OUTPUT
+VS A2 +IN 2.2k -VS WR +VS 2.2k
10k
10k
REF
+VS
-VS
DGND
06287-050
-VS
-VS
Figure 5. Simplified Schematic
The AD8253 is a monolithic instrumentation amplifier based on the classic, three op amp topology as shown in Figure 5. It is fabricated on the Analog Devices, Inc. proprietary iCMOS process that provides precision, linear performance ,and a robust digital interface. A parallel interface allows users to digitally program gains of 1, 10, 100, and 1000. Gain control is achieved by switching resistors in an internal, precision, resistor array (as shown in Figure 5). Although the AD8253 has a voltage feedback topology, gain bandwidth product increases for gains of 1, 10, and 100 because each gain has its own frequency compensation. This results in maximum bandwidth at higher gains. All internal amplifiers employ distortion cancellation circuitry and achieve high linearity and ultralow THD. Laser trimmed resistors allow for a maximum gain error of less than 0.03% for G = 1, and minimum CMRR of 120 dB for G = 1000. A pinout optimized for high CMRR over frequency enables the AD8253 to offer CMRR over frequency of 80 dB at 50 kHz (G = 1). The balanced input reduces the parasitics that, in the past, had adversely affected CMRR performance.
Transparent Gain Mode
The easiest way to set the gain is to program it directly via a logic high or logic low voltage applied to A0 and A1. Figure 6 shows an example of this gain setting method, referred to throughout the data sheet as transparent gain mode. Tie WR to the negative supply to engage transparent gain mode. In this mode, any change in voltage applied to A0 and A1 from logic low to logic high, or vice versa, immediately results in a gain change. Table 5 is the truth table for transparent gain mode and Figure 6 shows the AD8253 configured in transparent gain mode.
GAIN SELECTION
This section shows users how to configure the AD8253 for basic operation. Logic low and Logic high voltage limits are listed in the Specifications section. Typically, logic low is 0 V and logic high is 5 V; both voltages are measured with respect to DGND. Refer to the specifications table (Table 2) for the permissible voltage range of DGND. The gain of the AD8253 can be set using two methods.
Rev. prA | Page 8 of 10
Figure 6. Transparent Gain Mode, A0 and A1 = High, G = 1000
Preliminary Technical Data
Table 5. Truth Table Logic Levels for Transparent Gain Mode
WR -VS -VS -VS -VS A1 Low Low High High A0 Low High Low High Gain 1 10 100 1000 WR High to Low High to Low High to Low High to Low Low to Low Low to High High to High
1
AD8253
Table 6. Truth Table Logic Levels for Latched Gain Mode
A1 Low Low High High X1 X1 X1 A0 Low High Low High X1 X1 X1 Gain Change to 1 Change to 10 Change to 100 Change to 1000 No Change No Change No Change
Latched Gain Mode
Some applications have multiple programmable devices such as multiplexers or other programmable gain instrumentation amplifiers on the same PCB. In such cases, devices can share a data bus. The gain of the AD8253 can be set using WR as a latch, allowing other devices to share A0 and A1. Figure 7 shows a schematic using this method, known as latched gain mode. The AD8253 is in this mode when WR is held at logic high or logic low, typically 5 V and 0 V, respectively. The voltages on A0 and A1 are read on the downward edge of the WR signal as it transitions from logic high to logic low. This latches in the logic levels on A0 and A1, resulting in a gain change. See the truth table listing in Table 6 for more on these gain changes.
X = don't care.
Upon power-up, the AD8253 defaults to a gain of 1 when in latched gain mode. In contrast, if the AD8253 is configured in transparent gain mode, it starts at the gain indicated by the voltage levels on A0 and A1 upon power-up.
Timing for Latched Gain Mode
In latched gain mode, logic levels at A0 and A1 have to be held for a minimum setup time, tSU, before the downward edge of WR latches in the gain. Similarly, they must be held for a minimum hold time of tHD after the downward edge of WR to ensure that the gain is latched in correctly. After tHD, A0 and A1 may change logic levels but the gain does not change (until the next downward edge of WR). The minimum duration that WR can be held high is t WR-HIGH, and t WR-LOW is the minimum duration that WR can be held low. Digital timing specifications are listed in Table 2. The time required for a gain change is dominated by the settling time of the amplifier. A timing diagram is shown in Figure 8. When sharing a data bus with other devices, logic levels applied to those devices can potentially feed through to the output of the AD8253. Feedthrough can be minimized by decreasing the edge rate of the logic signals. Furthermore, careful layout of the PCB also reduces coupling between the digital and analog portions of the board.
Figure 7. Latched Gain Mode, G = 1000
tWR-HIGH
WR
tWR-LOW
tSU
A0, A1
tHD
06287-053
Figure 8. Timing Diagram for Latched Gain Mode
Rev. prA | Page 9 of 10
AD8253 OUTLINE DIMENSIONS
3.10 3.00 2.90 3.10 3.00 2.90 PIN 1 0.50 BSC 0.95 0.85 0.75 0.15 0.05 0.33 0.17 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA 1.10 MAX 8 0
10 6
Preliminary Technical Data
1
5
5.15 4.90 4.65
SEATING PLANE
0.23 0.08
0.80 0.60 0.40
Figure 9. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters
ORDERING GUIDE
Model AD8253ARMZ1 AD8253ARMZ-RL1 AD8253ARMZ-R71 AD8253-EVALZ1
1
Temperature Range -40C to +85C -40C to +85C -40C to +85C
Package Description 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP Evaluation Board
Package Option RM-10 RM-10 RM-10
Branding Y0K Y0K Y0K
Z = RoHS compliant part.
Rev. PrA | Page 10 of 10
PR06983-0-9/07(PrA)

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